1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for predicting electromigration lifespan of conductor structures.
2. Description of the Related Art
Conventional semiconductor devices typically include a semiconductor substrate, a plurality of insulating and conductive levels formed thereon having a conductive interconnection pattern comprising features and spacings, such as a plurality of spaced apart conductive lines, and several types of conductive interconnection lines, such as bus lines, power supply lines and clock lines. The various conductor lines may have linewidths at or above the minimum widths specified in the design rules of the semiconductor device.
A limitation on the lifetime and reliability of conventional semiconductor devices attributed to conductive interconnection lines is due to electromigration. The phenomenon of electromigration involves the flow of electrons causing the migration of atoms, thereby generating voids and hillocks. The formation of voids creates an opening in a conductive interconnection line, thereby decreasing the performance of the interconnection line. The formation of voids generates areas of increased resistance which undesirably reduce the speed of a semiconductor device. The voids may eventually span the entire cross-section of a line and lead to an open circuit. Thus, electromigration constitutes a limitation on the lifetime of a conductive interconnection line as well as the performance of the semiconductor device.
Electromigration in a metal interconnection line can be characterized by the movement of ions induced by a high electrical current density. The continual miniaturization of feature sizes of semiconductor devices increases current density, which can causes an attendant increase in electromigration induced metallization failures.
The basic physics of electromigration behavior for small conductor lines is relatively well known. The specific lifetime for a given integrated manufacturing process is measured during the technology qualification, which must be completed prior to the start of manufacturing. Accordingly, chip designers create design rules for conductor lines that take into consideration electromigration lifespan. However, there remains the need to verify the electromigration assumptions built into design rules. The verification is always done prior to fully qualifying a wafer design for commercial production. However, subsequent testing is frequently done to verify the impacts of, for example, the use of a new lithography or material deposition tool in wafer processing.
A conventional technique uses test structures built into a semiconductor wafer. In one conventional variation, scanning electron microscopy is used to examine line widths of the test structure and a comparison is then made with the design rule. Subsequently the test structure is physically tested to examine electromigration lifespan. This discrete test structure is built to model each conductor line width. The test structures are often built into the scribe lines of a wafer. At the stage of wafer dicing, the test structures are cut out as so-called chiplets. The chiplets are then mounted in a package of one sort or another and then subjected to electromigration testing. To simulate in a reasonable time period the electromigration lifespan of a conductor of a given line width that may last many years, the chiplet is subjected to highly elevated temperatures and current densities for a period of hours or weeks. The time to failure in hours or weeks is then extrapolated out to the actual multi-year lifespan of the modeled conductor line.
A difficulty associated with the first conventional technique is that scanning electron microscopy may not be able to accurately resolve very fine line widths. Certain inefficiency issues are associated with the second conventional technique since discrete chiplets are used for each conductor line width. This requires more chip area and more complex testing of larger numbers of chiplets.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.